Latest generation FPGAs determine the future usage of FIR filters. Their DSP blocks are able to implement fixed-point data types for efficient computations. The systolic multiply-accumulate architecture is utilized for various order and parallel multiple channel to efficiently handle resource and timing considerations. Implementing various order filter taps, resource and latency of the particular architecture of Xilinx Artix-7 (XC7A100T-1CSG324C) series with the clock frequency of 100 MHz and 12 bit input and 12 bit output is observed. The proposed design also shows that this design is suitable for multichannel parallel implementation such as power electronics applications in smart grids.