In order to compare the main electrical parameters such as ideality factor (n), barrier height (BH) (Phi(I-V)), series (R-s) and shunt (R-sh) resistances and energy density distribution profile of surface states (N-ss), the Au/n-Si (MS) Schottky diodes (SDs), with and without interfacial (Ca1.9Pr0.1Co4Ox) layer were obtained from the current Z voltage (I-V) measurements at room temperature. The other few electrical parameters such as Fermi energy level (E-F), BIT (Phi(C-V)), Re and voltage dependence of N-ss profile were also obtained from the capacitance voltage (C-V) measurements. The voltage dependence of N-ss profile has two distinctive peaks in the depletion region for two diodes and they were attributed to a particular distribution of N-ss located at metal semiconductor (MS) interface. All of these results have been investigated at room temperature and results have been compared with each other. Experimental results confirmed that interfacial (Ca1.9Pr0.1Co4Ox) layer enhanced diode performance in terms of rectifier rate (RR = I-F/I-R at +/- 3.4 V), N-ss (at 0.5 eV) and Rsh (-3.4 V) with values of 265, 5.38 x 10(13)eV(-1).cm(-2) and 7.87 x 10(4) Omega for MS type Schottky barrier diode and 2.56 x 10(6), 1.15 x 10(13) eV(-1).cm(-2) and 7.50 x 10(8) Omega for metal insulator semiconductor (MIS) type SBD, respectively. It is clear that the rectifying ratio of MIS type SBD is about 9660 times greater than MS type SBD. The value of barrier height (BIT) obtained from C-V data, is higher than the forward bias I-V data and it was attributed to the nature of measurements. These results confirmed that the interfacial (Ca1.9Pr0.1Co4Ox) layer has considerably improved the performance of SD.