Although the multilevel inverter topologics are comprehensively studied in power conversion issues, novel topologies are still being sought in order to decrease required semiconductors for same output levels that are currently obtained with classical multilevel topologies. Several studies have been reported in the literature on multilevel inverter topologies and control techniques. However, the cascaded multilevel inverter topology is one of the most widely studied topology to increase the output levels, asymmetrical topology in cascaded multilevel allow to increase output level with less switches. This paper presents a solution to improve efficiency of a cascaded multilevel inverter by converting it to an asymmetrical topology and proposing a control scheme to increase output voltage levels. The proposed 24-channel phase shifted sinusoidal pulse width modulation (PS-SPWM) circuit generates switching orders to be applied to the asymmetrical H-bridge cells. The designed voltage source inverter (VSI) is supplied with DC sources at V divided by 2V ratio to generate 7-level phase voltages at the output. The multilevel inverter is commutated at 2.5 kHz and 5 kHz switching frequencies and total harmonic distortion (THD) ratios are analysed. While the line voltage THD and line current THD ratios are measured as 42.98% and 1.29% respectively at 2.5 kHz switching frequency (f(sw)), they are decreased to 14.49% and 0.29% by increasing f(sw) to 5 kHz. Due to harmonics are appear as side-bands around f(sw) and its multiples in the PS-SPWM, the decrement on THD ratios can be obtained by increasing the f(sw) to an adequate limit without requiring any filter.