Mapping application-specific topology to mesh topology with reconfigurable switches

Kullu P., AR Y., TOSUN S., Ozdemir S.

IET COMPUTERS AND DIGITAL TECHNIQUES, vol.14, no.1, pp.9-16, 2020 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 14 Issue: 1
  • Publication Date: 2020
  • Doi Number: 10.1049/iet-cdt.2018.5202
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Academic Search Premier, PASCAL, Aerospace Database, Applied Science & Technology Source, Business Source Elite, Business Source Premier, Communication Abstracts, Compendex, Computer & Applied Sciences, INSPEC, Metadex, Civil Engineering Abstracts
  • Page Numbers: pp.9-16
  • Keywords: genetic algorithms, network-on-chip, network topology, fault tolerance, network routing, energy consumption, low-power electronics, mapping application-specific topology, reconfigurable switches, energy consumption, regular NoC topologies, fault-tolerance capabilities, chip area, irregular NoC topologies, two-step method, mesh topology, network-on-chip architecture, genetic algorithm, routing path, communicating nodes, ENERGY-AWARE, NETWORK, GENERATION, ALGORITHM
  • Gazi University Affiliated: Yes


When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors' method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.