This paper presents a digital signal processor (DSP) based algorithm to generate three-level output voltage using H-Bridge multilevel inverter (MU). The developed sinusoidal pulse width modulation (SPWM) scheme is employed to achieve lower harmonic contents in the output waveforms of inverter. Since SPWM scheme does not utilize vector positions, any pre-calculated switching states are not required. In addition to this advantage of conventional SPWM. modulators eliminate only base band harmonics due to regular control scheme. Therefore, neglecting the side band harmonics limits the efficiency of SPWM scheme. The harmonics located in the side bands of carrier frequency are also eliminated by the enhanced SPWM scheme proposed in this study. The validation of the modelled system is verified with the total harmonic distortion (THD) analyzes. The control algorithm is developed using TMS320F2812 DSP that is a 32-bit fixed-point processor operating at 150 MHz. The simulation and experimental results are compared to previous studies. The THD ratios of phase voltages and currents are measured loading the inverter with a three- phase 3 kW asynchronous motor. The lowest THD ratios of voltage and current are obtained at 1.9% and 0.4%, respectively. (C) 2011 Elsevier B.V. All rights reserved.