Correlation between barrier height and ideality factor in identically prepared diodes of Al/Bi4Ti3O12/p-Si (MFS) structure with barrier inhomogeneity

Cetinkaya H. G. , Yildirim M., Durmus P., Altindal Ş.

JOURNAL OF ALLOYS AND COMPOUNDS, cilt.721, ss.750-756, 2017 (SCI İndekslerine Giren Dergi) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 721
  • Basım Tarihi: 2017
  • Doi Numarası: 10.1016/j.jallcom.2017.06.037
  • Sayfa Sayıları: ss.750-756


This study aims to investigate electrical characteristics of identically prepared metal-ferroelectric-semiconductor (MFS) structures. Therefore a total number of 58 diodes were fabricated in the form of Al/Bi4Ti3O12/P-Si structure and then current-voltage (I-V) and admittance-voltage (C-V and G/omega-V) measurements were performed at room temperature. It was found that zero bias barrier height (Phi(Bo)) and ideality factor (n) show diode-to-diode variance. The value of n varied from 2.7 to 5.3 and such high values were attributed to the barrier height (BH) inhomogeneity, interfacial layer and surface states (N-ss). Similar behavior was observed for series resistance (R-s) values which were obtained by using Nicollian-Brews method. Other electrical parameters such as doping concentration of acceptor atoms (N-A), Fermi energy (E-F), and BH (Phi(B)) were extracted from reverse bias C-2-V characteristics. The experimental values of BH obtained from the forward bias I-V and reverse bias C-2-V characteristics varied from 0.69 to 0.84 eV and 0.75-0.93 eV and statistical analysis revealed mean BH values as 0.716 eV and 0.818 eV, respectively. We believe the variations in the electrical parameters are due to inhomogeneous interfacial layer and BH, non-uniformity of the interfacial traps or dislocations, and grain boundaries. (C) 2017 Elsevier B.V. All rights reserved.