In order to see effects of interfacial (with and without different graphene (GP) + Ca1.9Pr0.1Co4Ox-doped PVA) layer on the electrical characteristics of conventional Au/n-Si (MS) contacts. Therefore, Au/(GP + Ca1.9Pr0.1Co4Ox-doped PVA)/n-Si (MPS) structures were fabricated with different rates of (%3 GP, %7 GP) PVA and were fabricated on same n-Si wafer. Au/n-Si (MS), Au/PVA/n-Si, Au/%3GP + Ca1.9Pr0.1Co4Ox-doped PVA/n-Si and Au/%7GP + Ca1.9Pr0.1Co4Ox-doped PVA/n-Si structures were fabricated and their main electrical characteristics compared each other by using current-voltage (I-V) methods. The forward and reverse bias current voltage (I-V) characteristics of with and without GP + Ca1.9Pr0.1Co4Ox-doped PVA/n-Si at room temperature were studied to investigate its main electrical parameters. The energy density distribution profile of the interface states (N-ss) was obtained from the forward bias I-V data by taking into account voltage dependent ideality factor (n(v)) and effective barrier height (I broken vertical bar(e)) and they increase from at about mid-gap energy of Si to bottom of conductance band edge. In addition, voltage dependent profile of resistivity of the structure was obtained from I-V data for four different structures. The analysis of experimental results reveals that the existence of GP + Ca1.9Pr0.1Co4Ox-doped PVA interfacial layer improves the performance of MS structure. In order to determine the dominant current-transport mechanism (CTM) in the whole forward bias region of these structures, the double logarithmic forward bias I-V plots were also drawn. These plots exhibit two distinct linear region with different slopes which are corresponding to intermediate and high forward bias voltages. The slope of these plots show that in the region 1 (low biases) the dominant CTM is trap-charge-limited current (TCLC), whereas in the region 2 (high biases) is space-charge-limited current (SCLC) for four diodes.