Electrical characteristics of Au/PVP/n-Si structures using admittance measurements between 1 and 500 kHz


ALPTEKİN S., ALTINDAL Ş.

JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, vol.31, no.16, pp.13337-13343, 2020 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 31 Issue: 16
  • Publication Date: 2020
  • Doi Number: 10.1007/s10854-020-03887-6
  • Title of Journal : JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS
  • Page Numbers: pp.13337-13343

Abstract

In this study, Au/n-Si structures with PVP polymer interlayer were fabricated and characterized using capacitance/conductance-voltage-frequency (C/G-V-f) measurements. Obtained electrical parameters were found to be sensitive to frequency due to polymer interlayer, changes of traps/states (D-it/N-ss) level, interfacial/dipole polarization. The dispersion in C and G in depletion region is due toN(ss)/polarization, while the dispersion in accumulation region is due to interlayer/series resistance (R-s). The voltage-dependent profiles ofN(ss)andR(s)were derived using the methods of low-high frequency capacitance/Hill-Coleman and Nicollian-Brews, respectively. The width of depletion layer (W-d) and barrier height (phi(B)) values increase with increasing frequency almost linearly. On the other hand,R(s)decreases with increasing frequency whereas the maximum electric field (E-m) exhibits opposite behavior. The high frequency C/G-V plots were corrected to reveal theR(s)effect on them. The experimental results indicate that the growth of PVP interlayer by spin coating at the Au/n-Si interface yields a preferable and suitable device compared to devices with conventional insulating interlayer due to some advantages of polymer interlayers such as low-cost/weight, flexibility, and easy grown processes.